1. Field of the Invention
The present invention relates to the memory field. More specifically, the present invention relates to the reading of memory devices.
2. Description of the Related Art
Memory devices are commonly used to store information (either temporarily or permanently) in a number of applications; for example, in a non-volatile memory device the information is preserved even if a power supply is off. Typically, the memory device includes a matrix of memory cells (for example, consisting of floating gate MOS transistors); each memory cell has a threshold voltage that can be programmed to different levels representing corresponding logical values. Particularly, in a multi-level memory device each cell can take more than two levels (and then store a plurality of bits).
The logical values stored in selected cells of the memory device are read by comparing a current flowing through each memory cell with the ones provided by one or more reference cells (in a known condition). For this purpose, a suitable biasing voltage is applied to the selected memory cells and to the reference cells. However, the correctness of the reading operation strongly depends on the accuracy and the repeatability of the biasing voltage. This problem is particular acute in multi-level memory devices, wherein the safety margin for discriminating the different logical values is narrower.
A different technique is disclosed in U.S. Patent Application Publication No. 2004/0257876 (the entire disclosure of which is herein incorporated by reference). This document proposes the use of a biasing voltage having a monotone time pattern; preferably, the waveform of the biasing voltage consists of a ramp, which increases linearly over time with a constant slope. In this case, each selected memory cell and the reference cells turn on at different times (as soon as the biasing voltage reaches their threshold voltages). The temporal order of the tuning on of the memory cell with respect to the ones of the reference cells uniquely identifies the logical value stored therein. In this way, the precision of the reading operation is strongly improved and made independent of most external factors (such as the temperature).
However, the above-described technique requires that the biasing voltage should exhibit the desired time-pattern with a high accuracy; particularly, the biasing voltage should preferably change as much as possible linearly over time. Moreover, the biasing voltage that is applied to the selected memory cells and to the reference cells must have the same value, or at least the same slope.
For this purpose, the memory device is generally provided with a ramp generator receiving a model voltage (having the desired ramp-like pattern), which is created separately from a power supply voltage of the memory device; this model voltage is then applied to the selected memory cells and to the reference cells by means of a voltage follower. The biasing voltage is feedback-regulated according to the voltage that is actually measured at the reference cells.
A drawback of the solution known in that art is the high complexity of the ramp generator. Particularly, the above-described closed-loop involves a waste of area in a chip of semiconductor material wherein the memory device is typically integrated. In any case, operation of the ramp generator is slow; as a result, the slope of the biasing voltage must be quite low, thereby increasing the reading time of the memory device.